Modeling Data Transfer Signal Timings in Dame

infonnation transferred, refer to the accompanying paper on This paper discusses the timing interface design subsystem in data transfer interface design [6]. To transfer state or timing DAME (Design A utomation of M icroprocessor based infonnation, a timing reference is always required. When systems, using an Expert system approach). The timing connecting two devices, this timing reference must somehow design subsystem ensures that all signals produced by the be transferred from one device to another without violating interface between components meet the required timing any of the timing specifications. This reference can be specifications. A main goal of the timing and signal model is generated either with the same signal, or with a different the abstraction of common features found in the data transfer signal than the signal carrying the timing information. timings of most components. This allows relatively few 2 1 S . I R t t . I be ed " h . f d . h . h I .Igna epresen a Ion common fU es to us lor t e Inter ace eslgn w IC app y ..., II t Th .. t d th t .. d Devices such as microprocessors and memorIes have signal to a componen S. IS paper In ro uces e Imlng an. , I d I d t .f th d t t " t .. f pIns. Signal pInS are used to transfer Information to or from a signa mo e use o specl yea a ransler Imlng o ... . t E I f th d .ff t device In the form of electrIcal voltage levels. At anyone microprocessor componen s. xamp es o e I eren t .. t I t I t . d th d . t t poInt In time, a signal pm has a certaIn electrIcal state which Imlng pro oco emp a es are given, an e eslgn s ra egy ., .. d b th t .. d . b t . d . sed corresponds to some logic state. The logic state of a signal IS use ye Imlng eslgn su sys em IS ISCUS .. a characterIstic of the signal that can be propagated through a wire, or through a logic circuit. The following logic states are defined for signals,